/*
 * =====================================================================================
 *
 *       Filename:  board.h
 *
 *    Description:  
 *
 *        Version:  1.0
 *        Created:  03/17/2012 02:19:11 PM
 *       Revision:  none
 *       Compiler:  arm-linux-gcc 4.4
 *
 *         Author:  Chen Yuheng (Chen Yuheng), chyh1990@163.com
 *   Organization:  Tsinghua Unv.
 *
 * =====================================================================================
 */


#ifndef  MACH_BOARD_AT91_H
#define  MACH_BOARD_AT91_H

#define AT91SAMPB_IO_START 0xF0000000
#define AT91SAMPB_UART0 0xFFFFEE00

#define AT91C_BASE_AIC            (0xFFFFF000)  // (AIC) Base Address


// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
// *****************************************************************************
// *** Register offset in AT91S_AIC structure ***
#define AIC_SMR         ( 0)    // Source Mode Register
#define AIC_SVR         (128)   // Source Vector Register
#define AIC_IVR         (256)   // IRQ Vector Register
#define AIC_FVR         (260)   // FIQ Vector Register
#define AIC_ISR         (264)   // Interrupt Status Register
#define AIC_IPR         (268)   // Interrupt Pending Register
#define AIC_IMR         (272)   // Interrupt Mask Register
#define AIC_CISR        (276)   // Core Interrupt Status Register
#define AIC_IECR        (288)   // Interrupt Enable Command Register
#define AIC_IDCR        (292)   // Interrupt Disable Command Register
#define AIC_ICCR        (296)   // Interrupt Clear Command Register
#define AIC_ISCR        (300)   // Interrupt Set Command Register
#define AIC_EOICR       (304)   // End of Interrupt Command Register
#define AIC_SPU         (308)   // Spurious Vector Register
#define AIC_DCR         (312)   // Debug Control Register (Protect)
#define AIC_FFER        (320)   // Fast Forcing Enable Register
#define AIC_FFDR        (324)   // Fast Forcing Disable Register
#define AIC_FFSR        (328)   // Fast Forcing Status Register
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
#define AT91C_AIC_PRIOR           (0x7 <<  0)   // (AIC) Priority Level
#define 	AT91C_AIC_PRIOR_LOWEST               (0x0)      // (AIC) Lowest priority level
#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7)      // (AIC) Highest priority level
#define AT91C_AIC_SRCTYPE         (0x3 <<  5)   // (AIC) Interrupt Source Type
#define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  (0x0 <<  5)      // (AIC) Internal Sources Code Label Level Sensitive
#define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   (0x1 <<  5)      // (AIC) Internal Sources Code Label Edge triggered
#define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       (0x2 <<  5)      // (AIC) External Sources Code Label High-level Sensitive
#define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    (0x3 <<  5)      // (AIC) External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
#define AT91C_AIC_NFIQ            (0x1 <<  0)   // (AIC) NFIQ Status
#define AT91C_AIC_NIRQ            (0x1 <<  1)   // (AIC) NIRQ Status
// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
#define AT91C_AIC_DCR_PROT        (0x1 <<  0)   // (AIC) Protection Mode
#define AT91C_AIC_DCR_GMSK        (0x1 <<  1)   // (AIC) General Mask


// *****************************************************************************
//              SOFTWARE API DEFINITION  FOR Usart
// *****************************************************************************
// *** Register offset in AT91S_USART structure ***
#define US_CR           ( 0)    // Control Register
#define US_MR           ( 4)    // Mode Register
#define US_IER          ( 8)    // Interrupt Enable Register
#define US_IDR          (12)    // Interrupt Disable Register
#define US_IMR          (16)    // Interrupt Mask Register
#define US_CSR          (20)    // Channel Status Register
#define US_RHR          (24)    // Receiver Holding Register
#define US_THR          (28)    // Transmitter Holding Register
#define US_BRGR         (32)    // Baud Rate Generator Register
#define US_RTOR         (36)    // Receiver Time-out Register
#define US_TTGR         (40)    // Transmitter Time-guard Register
#define US_FIDI         (64)    // FI_DI_Ratio Register
#define US_NER          (68)    // Nb Errors Register
#define US_IF           (76)    // IRDA_FILTER Register
#define US_RPR          (256)   // Receive Pointer Register
#define US_RCR          (260)   // Receive Counter Register
#define US_TPR          (264)   // Transmit Pointer Register
#define US_TCR          (268)   // Transmit Counter Register
#define US_RNPR         (272)   // Receive Next Pointer Register
#define US_RNCR         (276)   // Receive Next Counter Register
#define US_TNPR         (280)   // Transmit Next Pointer Register
#define US_TNCR         (284)   // Transmit Next Counter Register
#define US_PTCR         (288)   // PDC Transfer Control Register
#define US_PTSR         (292)   // PDC Transfer Status Register


//#define PL011_RXFF    (1<<6)
#define AT91C_US_RXRDY            (0x1 <<  0)   // (DBGU) RXRDY Interrupt
#define AT91C_US_TXRDY            (0x1 <<  1)   // (DBGU) TXRDY Interrupt
#define AT91C_US_ENDRX            (0x1 <<  3)   // (DBGU) End of Receive Transfer Interrupt
// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
#define AT91C_US_RSTRX            (0x1 <<  2)   // (DBGU) Reset Receiver
#define AT91C_US_RSTTX            (0x1 <<  3)   // (DBGU) Reset Transmitter
#define AT91C_US_RXEN             (0x1 <<  4)   // (DBGU) Receiver Enable
#define AT91C_US_RXDIS            (0x1 <<  5)   // (DBGU) Receiver Disable
#define AT91C_US_TXEN             (0x1 <<  6)   // (DBGU) Transmitter Enable
#define AT91C_US_TXDIS            (0x1 <<  7)   // (DBGU) Transmitter Disable
#define AT91C_US_RSTSTA           (0x1 <<  8)   // (DBGU) Reset Status Bit

//extern macro
//
//CONFIG

#define SDRAM0_START 0x70000000
#define SDRAM0_SIZE  (0x8000000) //128M

#define IO_SPACE_START AT91SAMPB_IO_START
#define IO_SPACE_SIZE  0x10000000

#define KERNEL_PHY_BASE 0x70100000

#ifndef __ASSEMBLY__

#define UART0_TX 		((volatile unsigned char*) (AT91SAMPB_UART0+DBGU_THR))
//MUST be identical to linker script
#define INITIAL_LOAD    ((volatile uintptr_t *) (0x73f01000))

#endif

#endif  
